1. Field of the Invention
The present invention relates to a processor system which includes at least two processors and is capable of switching an operation mode between “lock step mode” for causing the at least two processors to execute the same instruction stream and “free step mode” for causing the at least two processors to execute different instruction streams, and to an operation mode switching method for the processor system.
2. Description of Related Art
There has been known a processor system which includes at least two processors (also referred to as processor cores) and is capable of switching an operation mode of the at least two processors between “lock step mode” and “free step mode”. Such a processor system is disclosed by, for example, Weiberle et al. (JP 2008-518338 A (corresponding International Patent Publication No. WO/2006/045775)) and Barr et al. (JP 2006-302289 A (corresponding US Patent Application Publication No. 2006/0245264)). In the lock step mode, two or more processors execute the same processing, and their execution results are compared with each other, thereby detecting occurrence of an error. Meanwhile; in the free step mode, two or more processors execute different processings, thereby improving the overall performance.
In addition, Safford et al. (JP 2005-302020 A (corresponding US Patent Application Publication No. 2005/0240811)) discloses a configuration for supplying the same data to first and second processors from an external circuit when the first and second processors execute the same instruction stream in the lock step mode. Specifically, Safford et al. discloses a configuration in which a selection circuit is disposed between an external circuit and a data reception unit included in the second processor. The selection circuit of the second processor is connected with a branch line from an input signal line for the first processor. While the first and second processors are executing the same instruction stream in the lock step mode, signals supplied from the external circuit to the first processor are branched to be also supplied to the selection circuit of the second processor. By controlling the selection circuit, the same data as that of the first processor is also supplied to the second processor.